1. Field of the Invention
Embodiments of the present invention relate to a method for manufacturing a semiconductor device. More particularly, embodiments of the present invention relate to a method for forming fine semiconductor patterns device with reduced and varying pitch therebetween using a hard mask in a double patterning process.
2. Description of the Related Art
In general, manufacturing of highly integrated semiconductor devices may require formation of a large number of miniaturized elements, e.g., semiconductor patterns, and integration thereof within a small area. Conventional formation of semiconductor patterns, e.g., interconnect patterns, may be achieved via, e.g., photolithography and film patterning. Integration of semiconductor devices in a small area may require a reduced pitch therebetween, i.e., a reduced sum of a width of one pattern and a width of one space between adjacent patterns.
Reducing a pitch between adjacent semiconductor patterns may be limited when using a photolithography process due to resolution restrictions, e.g., when forming a line and space (L/S) pattern on a substrate. Accordingly, attempts have been made to form semiconductor patterns via a hard mask pattern using a double patterning process, i.e., a process using separate masks to form two patterns. However, the conventional double patterning process for forming patterns with a varying pitch therebetween, e.g., when forming simultaneously a relatively high density pattern in a cell array region and a relatively low density pattern in a peripheral circuit area, may be complex, and may require different etch rates and depths, thereby causing non-uniformities and electrical defects.
Further, when copper (Cu) having a low resistivity is used as a material for fine patterns of a semiconductor, a damascene process may be used, i.e., formation of negative patterns in an insulating material to facilitate deposition of metal in spaces therebetween. However, when conventional double patterning is used to form fine patterns in the insulation material for a subsequent metal deposition, a reduced pitch between adjacent patterns may provide uneven and/or inaccurate pattern profiles, and may potentially trigger a pattern collapse and/or electrical failures. Accordingly, there exists a need for a method of forming a plurality of fine semiconductor patterns with reduced pitch therebetween by way of a double patterning.